Prior art techniques for carrying out division by approximation using a multiplier are disclosed in U.S. Pat. No. 3,828,175 issued to Amdahl et al.
For increasing the multiplication speed, the arithmetic apparatus uses a multiplier in addition to an adder. Further, for increasing the speed of division and square root extraction, a method of approximation is adopted and the approximation is performed by the multiplier.
One known method of approximation is Newton-Raphson iteration. Newton-Raphson iteration is a method for solving a function using an equation for a tangent to the function. Specifically, the function f(x) is solved by solving the following recurrence formula ##EQU1##
Using this method for dividing A by B, we first rewrite A.div.B as ##EQU2## and use Newton-Raphson iteration to find 1/B.
Given that f(x)=B-(1/x)=0, the recurrence formula is as follows: EQU x.sub.i+1 =x.sub.i .multidot.(2-Bx.sub.i) (3)
Thus, using this method, division can be conducted using only multiplication and subtraction.
In the case of square root extraction, given that EQU f(x)=A-x.sup.2 =0 (4),
the recurrence formula is ##EQU3## leaving a division term A/x.sub.i. Then, using the relation ##EQU4## 1/A is obtained by Newton-Raphson iteration.
Given that ##EQU5## the recurrence formula is ##EQU6## wherein it becomes possible to obtain the square root only by multiplication, subtraction and a 1/2 times-calculation. The 1/2 times calculation can be realized in a binary computer simply by a shift operation.
Where multiplication, division and square root extraction are conducted by the arithmetic unit, the size of the arithmetic unit required becomes larger as the scale of the calculation increases and the number of bits that have to be handled increases. On the other hand, where a small scale calculation of, say, a width of 33 bits is performed using a large scale arithmetic unit of a width of 66 bits, the time required for the small scale calculation will be the same as that needed for the large scale calculation. This means there is a tradeoff between a scale increase in the arithmetic unit for speed-up of large scale calculations accompanied by difficulty in high-speed processing for the small scale calculations and a scale increase in the arithmetic unit for speed-up of small scale calculations accompanied by difficulty in high-speed processing for the large scale calculations.
Thanks to advances in semiconductor device integration technology, it is no longer difficult to increase the scale of arithmetic units provided on a small chip. There is, however, a strong demand for speeding up the operation of the arithmetic unit and thus an urgent need to solve the aforesaid tradeoff problem.
In addition, since the realization of the high-speed processing requires the constituent devices of the arithmetic unit to operate in parallel, counter-measures are also necessary in this direction.